IBM PPC440X5 Manuale Utente Scaricare il pdf (Pagina 478)

100

101

DCDBTRH

Data Cache Debug Tag Register High

PPC440x5 CPU Core User’s Manual Preliminary

Page 478 of 589

regsumm440core.fm.

September 12, 2002

DCDBTRH

SPR 0x39D Supervisor Read-Only

See dcread Operation on page 127.

Figure 10-13. Data Cache Debug Tag Register High (DCDBTRH)

0:23 TRA Tag Real Address

Bits 0:23 of the lower 32 bits of the 36-bit real

address associated with the cache line read by

dcread.

24 V

Cache Line Valid

0 Cache line is not valid.

1 Cache line is valid.

The valid indicator for the cache line read by

dcread.

25:27 Reserved

28:31 TERA Tag Extended Real Address

Upper 4 bits of the 36-bit real address associated

with the cache line read by dcread.

0 23 24 25 27 28 31

TRA

TERA

1 2 ... 473 474 475 476 477 478 479 480 481 482 483 ... 589 590

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IBM PPC440X5 Manuale Utente Pagina 478

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